| HW# | Due Date | Assignments |
2/9W |
Interview someone who makes purchasing decision about the type of computers they use in their workplace. What are the typical criteria used by these decision makers, and what types of computers do they buy now versus what types of hardware would they expect to buy three years from now? | |
| 2 | 2/14M | Prepare a table summarizing "current" configuration for each computer class |
| 3 | 2/23W | Burd Textbook Research Problem: #2, Page 196 |
| 4 | 3/6M Solution |
Burd Textbook: Review Problems(Page 243): #2, #8, #9 & #11 Problems & Excerses (Page 244): #2 (show your work) |
| 5 | 3/20M Solution |
Burd Textbook - Review Questions(Page 280): #1 thru #4, and #7 thru #11 |
A bus master is any device that can initiate a transfer across the bus. Allowing devices other than the CPU to be bus masters frees CPU cycles to perform other tasks. It also allows a form of parallelism in which peripheral to peripheral data transfers can occur simultaneously with instruction execution.
3. What characteristics of the CPU and of the system bus should be balanced to obtain maximum system performance?
The width of the data bus should equal or exceed CPU word size. The bus clock rate should match the CPU clock rate, though this is difficult or impossible to achieve.
An interrupt is a signal to the operating system that a request or event has occurred that requires its attention.
Interrupts are numeric codes and can be generated by peripheral devices, an explicit software instruction, or the CPU itself. Peripheral device interrupts are sent over the system bus, detected by the CPU, and placed in an interrupt register. Software and CPU-generated interrupts are placed directly in the interrupt register by the CPU. The CPU detects an interrupt by checking the contents of the interrupt register after each execution cycle. If an interrupt is present the CPU suspends the current program by performing a PUSH operation. It then branches to the supervisor, which looks up the interrupt code in a table and calls the interrupt handler address it finds there. When the interrupt handler returns to the supervisor a POP operation is performed, which activates the program that was executing when the interrupt was detected.
7. What is the difference between a physical access and a logical access?
A physical access describes the storage location to be read or written in terms of the physical organization of storage locations (e.g., track, sector, and head for a disk drive). A logical access assumes that the location to be read or written is contained within a linear address space. Thus, the location is described by a single unsigned integer.
8. What functions does a device controller perform?
A device controller translates logical accesses into physical accesses and translates messages between the bus protocol and the protocol(s) used to control attached devices. A device controller may also perform multiplexing (i.e., allowing multiple devices to share a single bus port).
9. How are incompatibilities in communication parameters between the CPU and I/O and storage devices resolved?
Differences in control language are resolved by a device controller as it translates bus messages into device messages and vice versa. Differences in physical organization (i.e., deviations from the assumption of a linear address space) are resolved by a device controller as it translates logical accesses into physical accesses. Differences in communication speed and/or unit of data transfer are resolved by using a buffer located within the device or device controller.
10. What is a buffer? Why might one be used?
A buffer is an area of RAM implemented within a device controller, I/O device, or storage device. It is used to resolve differences in I/O unit size or speed of data production and consumption.
11. How may a cache be used to improve performance when reading data from a storage device? How may a cache be used to improve performance when writing data to a storage device?
A cache controller attempts to guess what data will be requested next and prefetch that data into the cache.
If the cache controller guesses correctly then data can be supplied more quickly. A cache controller confirms a write operation as soon as data is written to the cache but before it is written to the storage device. This improves the performance of a program that waits for write confirmation by reducing the interval between the write request and the write confirmation.
top 2. What is/are the difference(s) between static and dynamic RAM?The most important differences are speed and cost. Static RAM is five to ten times faster and approximately ten times more expensive. Static RAM is composed entirely of transistors. Dynamic RAM is composed of transistors and capacitors. The capacitors require frequent recharging which slows access time.
8. How is data stored and retrieved on a magnetic mass storage device?
For writing, current is routed through a read/write head which generates a magnetic charge at its tip. A bit area of a magnetic recording surface is placed in close proximity to the read/write head and a charge is induced in the surface material. The direction of current flow through the read/write head determines the polarity of the stored charge.
For reading, a bit area of the recording surface is placed in close proximity to the read/write head. The stored charge induces current to flow through the read write/head. A switch connected to the read/write head detects the direction of current flow to interpret it as a bit value.
9. Describe the factors that contribute to a disk drives average access time. Which of these factors are improved if spin rate is increased? Which are improved if recording density is increased?
Disk average access time is a combination of rotational delay, track-to-track seek time (head movement), and head-to-head switching time. Rotational delay is reduced if rotational speed is increased.
11. Why is the recording density of optical disks higher than the recording density of magnetic disks? What factor(s) limit this recording density?
A laser can be tightly focused to a narrow beam. Magnetic charge cannot be easily focused and an attempt to charge a very small area overwrites surrounding areas. Optical bit size is limited by the wavelength of the read laser and the amount of reflected light required to activate the read mechanism.
Problem #2 (Page 244)
2. Assume that a CPU has a clock rating of 400 MHz. Assume further that half of each clock cycle is used for fetching and the other half for execution.
One divided by 400,000,000 divided by 2 equals 1.25 nanoseconds.
b. How many wait states (per fetch) will the CPU incur if all of primary storage is implemented with 15 nanosecond static RAM?
15/2.5 = 6 wait states
c. How many wait states (per fetch) will the CPU incur if all of primary storage is implemented with 60 nanosecond "ordinary" dynamic RAM?
60/2.5 = 24 wait states